In the field of Very Large Scale Integration (VLSI) design employed by the semiconductor industry, due to the size and complexity of the designs of processing devices as well as the increasing scale of integration, design methodologies have been developed in order to simplify the process of designing the processing devices. In this respect, one known methodology has a flow that is hierarchical in nature, comprising two or more levels of design abstraction, for example: a top level and a block level.
The top level comprises defining block placements and so-called pin locations, and the block level comprises designing and placing the block instances, the placements and pinning of which were defined at the top level. The pin locations are defined in order to make connections between blocks for the communication of electrical signals therebetween.
So-called “top nets” are the connections or tracks between blocks defined at the top level. However, in order to minimise congestion, available routes or route resources are limited and require certain nets to be minimised. Also, where the fan out of such top nets is greater than one, it can be difficult to identify optimal routes for the top nets that fan out. When the routing of the top net is suboptimal, for example due to suboptimal placement of one or more pins, one or more of the top nets lead to a relatively long detour path that can result in suboptimal performance in respect of electrical signals communicated using the undesirably long detour path.
U.S. Pat. No. 6,298,468 relates to a placement-based optimisation method and apparatus for computer-aided circuit design that describes the modification of a pin placement based upon congestion and the “Centre of Gravity” (COG) of logic blocks used.
U.S. Pat. No. 6,567,967 relates to a method of designing large standard-cell based integrated circuits and describes block placement, pin placement modification and feedthrough creation to reduce top level congestion.